Choose timezone
Your profile timezone:
Powered by Indico
v3.3.3
The use of precision timing to measure time-of-flight or to distinguish events from the same bunch crossing has become a common feature in many modern and proposed collider experiments in the field of particle physics. One central challenge to achieving the required precision is the distribution of a precisely aligned clock to all the detector elements. While there are many places where this has been achieved for a few channels, this is not yet possible in a high-energy or nuclear-physics detector system, where there are hundreds of thousands, or more, channels. To address this challenge and push its boundary, we have been focused on the problem of distributing a reference clock with a precision of 100 femtoseconds (fs) or less. This will be an essential ingredient of any detector with a timing precision of less than 1 picosecond. Our program has focused on developing the tools to measure the phase of a reference clock to this level of precision, and manufacturing an ASIC capable of adjusting the phase of a clock in steps of 200 fs. Our original DDMTD was built with discrete high-speed flip-flops readout with an FPGA. With this technology, we have achieved a measurement precision of 100 fs. Using these tools, we have demonstrated the stabilization of a reference clock 1 km away from the source clock to sub-picosecond precision. As the next step, we have developed a phase detector ASIC on the TSMC 65nm node, rather than discrete off-the-shelf electronics — allowing us to optimize the design for the DDMTD application at chip-scale. This has enabled us to achieve a phase detection sensitivity of 30 fs. In this talk, I will give an overview of the current state of the art, the technologies that our group has developed and how it could be used in a real experiment to achieve a new level of timing precision.